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Analog-to-digital converter (ADC)
RM0008
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
A new ADC2 start is automatically generated after 28 ADC clock cycles
CONT bit can not be set in the mode since it continuously converts the selected regular
channel.
Note:
The application must ensure that no external trigger for injected channel occurs when
interleaved mode is enabled.
Figure 36. Slow interleaved mode on 1 channel
End of conversion on ADC2
Sampling
Conversion
ADC2
ADC1
Trigger
CH0
14 ADCCLK
cycles
28 ADCCLK
cycles
CH0
CH0
CH0
End of conversion on ADC1
11.9.5
Alternate trigger mode
This mode can be started only on an injected channel group. The source of external trigger
comes from the injected group mux of ADC1.
●
●
●
When the 1st trigger occurs, all injected group channels in ADC1 are converted.
When the 2nd trigger arrives, all injected group channels in ADC2 are converted
and so on.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are
converted.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are
converted.
If another external trigger occurs after all injected group channels have been converted then
the alternate trigger process restarts by converting ADC1 injected group channels.
Figure 37. Alternate trigger: injected channel group of each ADC
1st trigger
EOC, JEOC
3rd trigger
EOC, JEOC
(n)th trigger
Sampling
ADC1
ADC2
on ADC1
on ADC1
...
Conversion
EOC, JEOC
on ADC2
EOC, JEOC
on ADC2
214/995
2nd trigger
4th trigger
Doc ID 13902 Rev 9
(n+1)th trigger
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